FIG. 1 is a schematic diagram of a portion of a typical prior art integrated circuit output stage. Output stage 10 includes a plurality of output buffers, such as output buffers 11-1 and 11-2. As is well known in the art, typical output buffers include a P channel pull up transistor 12-1 having its source connected to Vcc, its drain connected to output lead 14-1, and its gate connected to control gate lead 11-1. A pull down transistor 13-1 has its gate connected to control gate lead 11-1, its drain connected to output lead 14-1, and its source connected to ground line 19. Each of the output buffers is connected in parallel between Vcc and ground line 19, and receives individual control signals on their gate control leads 11-1, 11-2, etc. in order to provide corresponding output signals on output leads 14-1, 14-2, etc., respectively.
The integrated circuit is contained within an integrated circuit package, such as a ceramic dual in line package (DIP) or a plastic DIP, for example. The leads of such packages include inductance such that ground line 19 on the integrated circuit is connected to external ground 18 through inductance 16. Unfortunately, this inductance causes ground bounce, i.e. a shift in the actual voltage on ground lead 19 due to changes in current flowing through inductor 16 to external ground 18.
The primary cause of such changes in current flowing through inductor 16 is switching of output buffers. Thus, for example, with the control signal applied to lead 11-2 held high in order to turn off pull up transistor 12-2 and turn on pull down transistor 13-2, output lead 14-2 is connected to ground lead 19. Ideally, the voltage on output lead 14-2 would be exactly equal to the externally supplied ground voltage on terminal 18, without any noise. Unfortunately, as other output buffers in the integrated circuit switch, current flowing to ground 18 through inductor 16 changes, thus changing the voltage on ground lead 19. This is depicted in FIG. 2.
With the voltage on control gate lead 11-2 held high, the output voltage on output lead 14-2 is low. With the voltage applied to control gate 11-1 low, the output voltage on output lead 14-1 is high, and no change in current is taking place through inductor 18, and thus ground lead 19 is at the same voltage level as external ground 18. When the voltage applied to control gate 11-1 rises, pull up transistor 12-1 turns off and pull down transistor 13-1 turns on. At this time, the output voltage on output terminal 14-1 falls since the charge stored in load capacitance 15-1 is discharged to ground 18 through conducting pull down transistor 13-1 and inductor 16. Thus, with a change in current I flowing through inductor 16, the voltage on ground lead 19 rises for a time and then falls as the current being discharged from load capacitance 15-1 decreases. The voltage on ground lead 19 with respect to external ground 18 is determined by the following equation ##EQU1## Vgnd=the voltage on ground level 19 with respect to external ground 18; L.sub.16 =the inductance of inductor 16; and ##EQU2##
This bounce in the voltage on ground lead 19 causes a similar bounce on the output voltage on output lead 14-2 which ideally should be held precisely at the voltage level of external ground 18. Furthermore, the portion of the ground bounce of ground lead 19 which extends below zero volts causes a similar excursion of output voltage 14-2 below zero volts.
The lead connecting the integrated circuit Vcc lead to an externally supplied Vcc also has inductance. This causes a Vcc bounce, i.e. a change in voltage on the Vcc lead of the integrated circuit within the package, in response to changes in current flowing through the inductance associated with the Vcc lead. As with changes in ground current, changes in Vcc current are primarily due to switching of the output buffers.
The effect of ground bounce is exacerbated when a number of output buffers switch simultaneously, as is often the case. Furthermore, as the speed of the device increases, output buffer switching speeds increase, thus causing increases in the time rate of change of currents as compared with slower devices.
Ground and Vcc bounce is undesirable for a number of reasons. First, it affects the voltage on output leads, possibly to the extent that a temporary change in logical levels is realized. Secondly, ground and Vcc bounce affects the ground and Vcc voltages applied to other portions of the integrated circuit, affecting their operation including possibly making operation fail all together. Furthermore, circuit designers must consider the fact that ground and Vcc bounce is present in their circuits and design their circuits more carefully in order to avoid operating failures due to ground and Vcc bounce.
It has been recognized that by providing a constant rate of change in ground and Vcc currents, ground and Vcc bounce can be minimized. This is described, for example, in IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October 1987, pages 744-746, and is depicted in FIGS. 3a and 3b. FIG. 3a shows a typical di/dt curve 30 depicting the change in ground voltage when an output switches. FIG. 3b shows the change in ground current accompanying the change in ground voltage shown in FIG. 3a. Without any control of the output switching, there is a relatively rapid change in current initially, which then tapers off. This nonlinearity in current increases ground and Vcc bounce. Ideally, di/dt can be made constant as shown in curve 31, thereby reducing the maximum ground bounce.
One technique for reducing ground bounce to a certain extent is shown in the schematic diagram of FIG. 4. FIG. 4 shows an output buffer including a pull up transistor 42, and two pull down transistors 43-a and 43-b. Pull down transistor 43-a is controlled by the signal applied to terminal 41 and pull down transistor 43-b is controlled by the signal applied to terminal 41 as delayed by delay means 45. Delay means 45 can be any convenient delay circuit, such as two inverters connected in cascade. The operation of the circuit of FIG. 4 has the effect of causing a certain amount of current to be discharged to ground through transistor 43-a during initial stages of switching and, at a specified time thereafter, drawing additional current through pull down transistor 43-b at a time later along curve 30 of FIG. 3, thereby tending to reduce the nonlinearity in current shown in curve 30. However, this technique requires additional components in the form of delay means 45.